Full adder cell with improved power efficiency
US11169779B2 · kind B2 · utility
0Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2020 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | May 12, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An adder circuit provides a first operand input and a second operand input to an XNOR cell. The XNOR cell transforms these inputs to a propagate signal that is applied to an OAT cell to produce a carry out signal. A third OAT cell transforms a third operand input and the propagate signal into a sum output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.