Systems, apparatuses, and methods for fused multiply add
US11169802B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2016 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | Oct 20, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3818
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, packed data elements of first and second packed data source operands are of a first, different size than a second size of packed data elements of a third packed data operand. Execution circuitry executes decoded single instruction to perform, for each packed data element position of a destination operand, a multiplication of a M N-sized packed data elements from the first and second packed data sources that correspond to a packed data element position of the third packed data source, add of results from these multiplications to a full-sized packed data element of a packed data element position of the third packed data source, and storage of the addition result in a packed data element position destination corresponding to the packed data element position of the third packed data source, wherein M is equal to the full-sized packed data element divided by N.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.