Patent · US Active

Tunable power save loop for processor chips

US11169841B2 · kind B2 · utility

0Cited by

6References

17Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

K Paul Muller · Beacon, US
William V. Huott · Holmes, US
Eberhard Engler · Rötteln, DE
Christopher R. Conklin · Stone Ridge, US
Stephanie Lehrer · Poughkeepsie, US
Andrew A. Turner · Colchester, US

Key dates

Filing date	Mar 17, 2020
Grant date	Nov 9, 2021
Priority date	—
Expiry date	Mar 17, 2040

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Aspects of the present invention disclose a method for avoiding overvoltages of a processor chip. The method includes one or more processors identifying one or more processing units of a computing device. The method further includes determining respective activity levels of one or more processing elements of the one or more processing units of the computing device. The method further includes determining respective voltages of the one or more processing units of the computing device. The method further includes regulating the respective voltages of the one or more processing units of the computing device based at least in part on the respective activity levels of the one or more processing elements.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.