Emulation latch to capture state
US11169895B2 · kind B2 · utility
0Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2020 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | Jan 27, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an approach to simulating an electronic device, a copy of a design under test is created. A delayed buffer for the copy is created, where the inputs to the design under test are stored in the delayed buffer. A test program is run on the design under test and the copy, where the test program running on the copy is delayed in time by the delayed buffer. Responsive to determining that an event has occurred on the design under test, the test program on the copy is halted. The cause of the event is determined by using the inputs stored in the delayed buffer to scan the copy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.