Pause communication from I/O devices supporting page faults
US11169929B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2018 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | Jan 1, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.