Methods, systems and apparatus to reduce memory latency when fetching pixel kernels
US11170463B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2018 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | May 21, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, apparatus, and articles of manufacture to reduce memory latency when fetching pixel kernels are disclosed. An example apparatus includes a prefetch kernel retriever to generate a block tag based on a first request from a hardware accelerator, the first request including first coordinates of a first pixel disposed in a first image block, a memory interface engine to store the first image block including a plurality of pixels including the pixel in a cache storage based on the block tag, and a kernel retriever to access two or more memory devices included in the cache storage in parallel to transfer a plurality of image blocks including the first image block when a second request is received including second coordinates of a second pixel disposed in the first image block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.