Techniques for reducing rock bottom leakage in memory
US11170845B1 · kind B1 · utility
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20Claims
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Key dates
| Filing date | Jul 14, 2020 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | Jul 14, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Certain aspects of the present disclosure are directed to a memory system. The memory system generally includes a word line (WL) driver circuit comprising a transistor coupled between a WL of a memory and a reference potential node. The memory system also includes a clamping circuit having logic configured to generate a control signal to drive a gate of the transistor such that the control signal is floating when the first head switch is open, and a first head switch coupled between a voltage rail and a supply input of the logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.