Fabrication method of integrated circuit semiconductor device
US11171038B2 · kind B2 · utility
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5References
20Claims
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Key dates
| Filing date | Jan 16, 2020 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | Jan 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabrication method of an integrated circuit semiconductor device includes: forming a plurality of low dielectric pattern apart from each other on a substrate, the plurality of low dielectric pattern having a lower dielectric constant than the substrate; after forming the low dielectric pattern, forming a flow layer to bury the low dielectric pattern on the substrate; forming an epitaxial layer on the flow layer; and forming a transistor in the substrate comprising the low dielectric pattern buried by the flow layer and in the epitaxial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.