Stacked microfluidic cooled 3D electronic-photonic integrated circuit
US11171075B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2017 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | Jun 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06589
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic-photonic integrated-circuit assembly comprises a carrier substrate (310) and one or more integrated-circuit dies (330, 340) bonded to one another so as to form a die stack with exterior surfaces corresponding to an outer surface of a first one of the integrated-circuit dies and to an outer surface of a second one of the integrated-circuit dies, where at least one of the integrated-circuit dies includes one or more integrated photonic devices. One or more channels or passages (320) are formed into the outer surface of the first one of the integrated-circuit dies, and a first surface of the carrier substrate (310) is bonded to the outer surface of the first one of the integrated-circuit dies, thereby enclosing the one or more channels or passages (320), The integrated-circuit dies are electrically connected to each other via electrically conductive through-wafer interconnects or electrically conductive through-wafer vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.