Transistor channel passivation with 2D crystalline material

US11171239B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Carl Naylor · Portland, US
• Abhishek A. Sharma · Hillsboro, US
• Mauro J. Kobrinsky · Portland, US
• Christopher J. Jezewski · Portland, US
• Urusa Alaan · Hillsboro, US
• Justin R. Weber · Portland, US

Key dates

• Filing date: Sep 13, 2019
• Grant date: Nov 9, 2021
• Expiry date: Sep 13, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D99/00

Abstract

Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g., <450° C.). The 2D material may be a chalcogenide of a metal present in the channel material (e.g., ZnSx or ZnSex) or of a metal absent from the channel material when formed from a sacrificial precursor.