Decoding method and apparatus
US11171673B2 · kind B2 · utility
1Cited by
1References
8Claims
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Key dates
| Filing date | Jul 8, 2020 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | Jul 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6561
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A decoding method and apparatus are provided, to improve a degree of parallelism in decoded bit decisions and reduce a decoding delay. The method includes: performing a hard decision on each LLR in an inputted LLR vector having a length of M to obtain a first vector, where M≤N and N is a length of to-be-decoded information; sequentially performing negation of some elements of the first vector to obtain L vectors; and then determining decoding results of the LLR vector based on the L vectors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.