Signal processing circuit and signal processing method
US11171767B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2021 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | Apr 12, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/23
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A signal processing circuit, which includes: a first clock source, configured to generate a first clock signal; a phase adjusting circuit, configured to receive the first clock signal, and to generate a second clock signal and a third clock signal, wherein the second clock signal and the third clock signal have different phases; an error compensating circuit, configured to compensate an input signal according to an error signal, to generate an compensated input signal; an error calculating circuit, configured to generate the error signal according to the first clock signal, the third clock signal and the compensated input signal; and a receiving end ADC (Analog to Digital Converter), configured to sample the compensated input signal according to the second clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.