Parallel decision feedback equalizer partitioned for high throughput
US11171816B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2020 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | Jul 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03636
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In some disclosed embodiments, a Decision Feedback Equalizer (DFE) processes multiple symbols in parallel using a novel architecture that avoids violating a timing constraint. The DFE comprises Feed-Back (FB) filters that can be configured to equalizing nonlinear phenomena. Using a Look-Up Table (LUT)-based implementation, the FB filters may implement complex nonlinear functions at low hardware complexity, low latency and low power consumption. A LUT-based implementation of the FB filter supports adaptive FB filtering to changing channel conditions by updating LUT content.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.