System and method for compacting test data in many-core processors
US11175338B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2019 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Dec 31, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/21
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for testing a many-core processor comprises grouping a plurality of cores in the processor into a plurality of super cores, wherein each super core comprises one or more scan chains that propagate through a respective super core. Further, the method comprises grouping the plurality of super cores into a plurality of clusters. The method also comprises comparing one or more scan chain outputs of respective super cores in each cluster using a network of XOR and OR gates to generate a single bit fault signature for each scan chain in a respective cluster and compacting the single bit fault signatures for each scan chain using a hybrid of spatial and temporal compactors to generate a single bit fault signature for each cluster. The method also comprises method of using a cost function to obtain hierarchical parameters to achieve optimized ATPG effort, area overhead and test time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.