System and method for managing testing and availability of critical components on system-on-chip
US11175340B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2021 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Feb 15, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31724
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system-on-chip (SoC) is disclosed. The SoC includes a set of fake fault injection circuits and a critical intellectual property (IP) core that includes first and second control circuits. The first and second control circuits are each operable in a test mode and a functional mode. The first and second control circuits are operated in the functional mode in lockstep in an absence of a fake fault input. In a presence of the fake fault input, one of the first and second control circuits is switched from the functional mode to the test mode. One of the first and second control circuits operating the test mode generates a fake fault response for the fake fault input. The critical IP core is determined as one of error-free and erroneous based on a detection of the generated fake fault response as one of error-free and erroneous, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.