Low-temperature drift ultra-low-power linear regulator
US11175686B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2020 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | May 12, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/618
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A low-temperature drift ultra-low-power linear regulator includes eight PMOS transistors, two resistors, two capacitors and three NMOS transistors. The eight PMOS transistors include PMOS transistor PM1 to PMOS transistor PM8. The two resistors include resistor R1 and resistor R2. The two capacitors include capacitor C1 and capacitor C2. The three NMOS transistors include NMOS transistor NM1, NMOS transistor NM2 and NMOS transistor NM3. From right to left, the linear regulator includes a PTAT voltage core starting circuit, a PTAT voltage core circuit, a negative temperature characteristic generating circuit and a driver stage closed-loop control circuit. PM5-PM8 form a feedback circuit. The feedback circuit clamps the current flowing through PM6 to be proportional to PM2 to obtain a temperature-stable output voltage, and can dynamically adjust the gate voltage of PM5 according to the change of load current to output different currents according to the load demand.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.