System and method of power mode management for a processor
US11175723B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2020 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Apr 20, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2284
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of power mode management for a processor providing safe and robust transitioning between normal and low power modes to meet low current requirements and to ensure accurate power mode transition communications. A two step process includes receiving a digital code, starting a standby entry timer, and receiving a low power request indication before timeout of the standby entry timer to ensure a valid request, and otherwise resetting upon timer timeout. A watchdog timer ensures that a maximum standby duration is not exceeded. An acknowledge timer ensures valid communication between modules of a power management IC. Memory elements ensure and maintain valid states of reset and safe state pins during standby. Self tests are performed in which test failure prevents transition to the low power mode. A power good indication ensures the processor that the supply voltages are suitable for both low power and normal operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.