Providing exception stack management using stack panic fault exceptions in processor-based devices
US11175926B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2020 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | May 7, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/481
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Providing exception stack management using stack panic fault exceptions in processor-based devices is disclosed. In this regard, a processor device defines a “stack panic fault exception” that may be raised upon execution of an exception handler store operation attempting to write state data into an exception stack, and provides a dedicated plurality of stack panic fault exception state registers in which stack panic fault exception state data may be saved. Upon detecting a first exception, the processor device transfers program control to an exception handler for the first exception. If a second exception occurs upon execution of a store operation in the exception handler, the processor device determines that the second exception should be handled as a stack panic fault exception, saves the stack panic fault exception state data in the stack panic fault exception state registers, and transfers program control to a stack panic fault exception handler.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.