Hardware accelerator for executing a computation task
US11175957B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2020 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Sep 22, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a hardware accelerator for executing a computation task composed of a set of operations. The hardware accelerator comprises a controller and a set of computation units. Each computation unit of the set of computation units is configured to receive input data of an operation of the set of operations and to perform the operation, wherein the input data is represented with a distinct bit length associated with each computation unit. The controller is configured to receive the input data represented with a certain bit length of the bit lengths and to select one of the set of computation units that can deliver a valid result and that is associated with a bit length smaller than or equal to the certain bit length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.