Extracting parasitic capacitance from circuit designs
US11176308B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2020 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Jun 19, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a target wiring layer, a first adjacent wiring layer above the target wiring layer, and a second adjacent wiring layer below the target wiring layer. Each adjacent wiring layer including crossing wires orthogonal to the target wiring layer. Modify a putative design of the integrated circuit by selecting a target wire; identifying lateral neighbors of the target wire; defining regions of the target wire where the lateral neighbors are homogeneous in cross-section; for each region of the target wire, calculating a wire pattern for the crossing wires; identifying segments within above and below portions of the wire pattern; for each above and below segment pair, obtaining a per-unit-length capacitance from a reduced pattern database; extracting a total parasitic capacitance from the per-unit-length pattern capacitances; and in response to an assessment of the impact of the total parasitic capacitance on circuit performance, producing a modified design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.