Auto-zero applied buffer for display circuitry
US11176888B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2020 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Jun 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0219
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system includes a pixel that emits light based on a signal provided to the pixel. The system may also include a buffer circuit having a differential pair stage, a cascade stage, and an output stage. The differential pair stage may receive a common mode voltage signal via a first switch in response to the first switch receiving a first signal that causes the first switch to close. The differential pair stage may couple a capacitor to the output stage via a second switch that operate based on a second signal, such that the capacitor reduces an offset provided by one or more circuit components in the differential pair stage, the cascade stage, the output stage, or any combination thereof. The differential pair stage may output the common mode voltage to the pixel via the output stage in response to the first signal being present.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.