Vertical transistor device comprising a two-dimensional (2D) material positioned in a channel region of the device and methods of making such vertical transistor devices

US11177182B2 · kind B2 · utility

Assignee

• GLOBALFOUNDRIES U.S. Inc. · US

Inventors

• Heng Yang · Fishkill, US
• David Pritchard · Beacon, US
• Kai Sun · Beijing, CN
• Hongru Ren · Mechanicville, US
• Neha Nayyar · Clifton Park, US
• Manjunatha Prabhu · Malta, US
• Elizabeth Strehlow · Malta, US
• Salvatore Cimino · Cohoes, US

Key dates

• Filing date: Jan 30, 2020
• Grant date: Nov 16, 2021
• Expiry date: Feb 28, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0195

Abstract

One illustrative vertical transistor device disclosed herein includes a channel region comprising at least one layer of a two-dimensional (2D) material, a bottom source/drain region, a top source/drain region and a gate structure positioned all around at least the at least one layer of a two-dimensional (2D) material.