Clock synthesis circuitry and associated techniques for generating clock signals refreshing display screen content
US11177793B2 · kind B2 · utility
0Cited by
5References
17Claims
0Family size
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Inventor
Key dates
| Filing date | Aug 9, 2018 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Aug 18, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05B45/325
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock synthesis circuit and method provides for precision controlling and programming a selected number of clock pulses (or simply “clocks”) fitted within time periods between two consecutive pulses of a so-called system heartbeat (SHB) timing signal. The disclosed embodiments have applicability in light emitting diode (LED) display driver integrated circuits (ICs) and, more generally, digital circuits including computer processors, microcontrollers, logic devices such as field-programmable gate arrays (FP-GA), and other logic circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.