Threshold tracking power-on-reset circuit
US11177803B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2020 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Sep 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power-on-reset (POR) circuit includes an NFET branch and a PFET branch. The NFET branch includes: an n-channel field effect transistor (NFET) having a first threshold voltage; and a first quiescent bias current source coupled between a supply terminal and the NFET. The PFET branch includes: a p-channel field effect transistor (PFET) having a second threshold voltage; and a second quiescent bias current source coupled between a ground terminal and the PFET. The POR circuit is configured to provide a POR signal at an output terminal based on: the first threshold voltage or the second threshold voltage, whichever is larger; and a voltage margin. The output terminal is coupled between the PFET branch and the second quiescent bias current source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.