Lane adaptation in high-speed serial links
US11177986B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2021 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Mar 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03636
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Adaptive equalizer circuitry including both a continuous time equalizer (CTE) and a discrete time equalizer (DTE) and a method of jointly adapting the CTE and DTE in lane adaptation. Jointly adaptation of the CTE and DTE is performed by adapting the DTE at each of a plurality of filter characteristic settings of the CTE and determining a figure of merit for signals filtered by the CTE and DTE at that condition. Adaptation of the DTE may be performed by dynamically adjusting a convergence coefficient based on a history of error gradients. After a figure of merit is determined for each of the plurality of CTE filter characteristics, a CTE filter characteristic setting is then selected based on those figure of merit values, for example at a CTE setting near a midpoint of an acceptable region of figure of merit values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.