Power management and transitioning cores within a multicore system from idle mode to operational mode over a period of time
US11181967B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2020 |
| Grant date | Nov 23, 2021 |
| Priority date | — |
| Expiry date | Jul 31, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a plurality of cores. Each core includes a processing unit, an on-chip memory (OCM), and an idle detector unit. Data is received and stored in the OCM. Instructions are received to process data in the OCM. The core enters an idle mode if the idle detector unit detects that the core has been idle for a first number of clocking signals. The core receives a command to process when in idle mode and transitions from the idle mode to an operational mode. A number of no operation (No-Op) commands is inserted for each time segment. A No-Op command prevents the core from processing instructions for a certain number of clocking signals. A number of No-Op commands inserted for a first time segment is greater than a number of No-Op commands inserted for a last time segment. After the last time segment no No-Op command is inserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.