Refresh circuit for use with integrated circuits
US11182106B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 21, 2018 |
| Grant date | Nov 23, 2021 |
| Priority date | — |
| Expiry date | Mar 21, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein are directed to an integrated circuit having a cache with memory components that store data with multiple addresses. The integrated circuit may include a controller that communicates with the cache to provide directives to the cache. The integrated circuit may include a refresh circuit that interprets the directives received from the controller to generate interpretation information based on determining one or more particular addresses of the multiple addresses that no longer need refreshing. The refresh circuit may further employ the interpretation information to skip the need for refreshing the one or more particular addresses pointing to the memory components in the cache that no longer need refreshing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.