Patent · US Active

Generating source and destination addresses for repeated accelerator instruction

US11182160B1 · kind B1 · utility

1Cited by

4References

20Claims

0Family size

Assignee

NXP USA, Inc. · US

Inventors

Maik Brett · Schweinhub, DE
Christian Tuschen · Munich, DE
Sidhartha Taneja · New Delhi, IN
Tejbal Prasad · Greater Noida, IN
Saurabh Arora · Gurugram, IN
Anurag Mithalal Jain · Bengaluru, IN
Pranshu Agrawal · New Delhi, IN
Mukul Aggarwal · Narnaul, IN
Ajay Sharma · Beaverton, US

Key dates

Filing date	Nov 24, 2020
Grant date	Nov 23, 2021
Priority date	—
Expiry date	Nov 24, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/3877
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method and circuit for a data processing system provide a hardware accelerator repeat control instruction (402A) which is executed with a hardware accelerator instruction (402B) to extract and latch repeat parameters from the hardware accelerator repeat control instruction, such as a repeat count value (RPT_CNT), a source address offset value (ADDR_INCR0), and a destination address offset value (ADDR_INCR1), and to generate a command to the hardware accelerator (205) to execute the hardware accelerator instruction a specified plurality of times based on instruction parameters from the hardware accelerator instruction by using the repeat count value to track how many times the hardware accelerator instruction is executed and by automatically generating, at each execution of the hardware accelerator instruction, additional source and destination addresses for the hardware accelerator from the repeat parameters until the hardware accelerator instruction has been executed the specified plurality of times by the hardware accelerator.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.