MIMD processor emulated on SIMD architecture
US11182170B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2019 |
| Grant date | Nov 23, 2021 |
| Priority date | — |
| Expiry date | Jun 6, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor having a SIMD architecture, including an array of elementary processors, each elementary processor being associated with an elementary memory cell, a central controller connected to the elementary processors by an instruction bus and a status bus. The central controller transmits a sequence of instructions in a loop, each instruction including a calculation flow indicator. Each elementary processor has an instruction filter that makes it possible to reject or take into account an instruction depending on the identifier it contains. This operating mode makes it possible to emulate a MIMD processor on a SIMD architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.