Processor and interrupt controller
US11182318B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2020 |
| Grant date | Nov 23, 2021 |
| Priority date | — |
| Expiry date | Mar 24, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4031
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide an interrupt controller in a processor, comprising: an interrupt sampling circuitry configured to receive one or more interrupts from one or more interrupt sources that are communicatively coupled to the interrupt controller; and an arbitration circuitry configured to select a to-be-responded interrupt from the received one or more interrupts, the arbitration circuitry comprising: a selection circuitry configured to select from the one or more interrupts a highest-priority interrupt that has a highest priority among the one or more interrupts; and a threshold comparison circuitry communicatively coupled to the selection circuitry, the threshold comparison circuitry configured to compare the priority of the highest-priority interrupt with a preset priority threshold, wherein the arbitration circuitry is configured to select the highest-priority interrupt as the to-be-responded interrupt in response to the threshold comparison circuitry determining that the priority of the highest-priority interrupt is higher than the preset priority threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.