Semiconductor memory device and memory state detecting method
US11183256B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2020 |
| Grant date | Nov 23, 2021 |
| Priority date | — |
| Expiry date | Jun 29, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to a certain embodiment, the semiconductor memory device includes a memory cell array, a control circuit, and a data register storing an erase verify fail flag. An erase target block is divided into word line groups. The control circuit includes: a counter configured to count the number of the erase verify fail flags to be output as a count value for each group; a plurality of counter registers configured to store the count value for each group; an arithmetic circuit configured to take a difference of the plurality of count values respectively stored in the plurality of counter registers and to output a result of the difference as a number of second fail flags; and a comparator configured to compare the number of criteria of the erase verify fail flag and the number of the second fail flags to be output as a memory state detected result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.