Component having a buffer layer and method for producing a component
US11183621B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2018 |
| Grant date | Nov 23, 2021 |
| Priority date | — |
| Expiry date | Jul 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/8514
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A component may include a semiconductor chip, a buffer layer, a connecting layer, and a metal carrier. The semiconductor chip may include a substrate and a semiconductor body arranged thereon. The metal carrier may have a thermal expansion coefficient at least 1.5 times as great as a thermal expansion coefficient of the substrate or of the semiconductor chip. The chip may be fastened on the metal carrier by the connecting layer, and the buffer layer may have a yield stress ranging from 10 MPa. The buffer layer may have a thickness ranging from 2 um to 10 um and adjoin the chip. The substrate and the metal carrier may have a higher yield strength than the buffer layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.