Clock detection and automatic PLL output bypass switching for an audio processor
US11184011B2 · kind B2 · utility
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1References
17Claims
0Family size
Assignee
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Key dates
| Filing date | May 29, 2020 |
| Grant date | Nov 23, 2021 |
| Priority date | — |
| Expiry date | May 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed for an audio processor that includes a clock detection circuit and a clock bypass circuit. According to various embodiments, the clock detection circuit can check and indicate the status of a main clock and upon detection of a loss of the main clock, the clock bypass circuit can switch the source of the main clock to an alternate source such as an on chip oscillator allowing the system to gracefully recover from the clock loss event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.