Impedance matching system for high speed digital receivers
US11184196B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2020 |
| Grant date | Nov 23, 2021 |
| Priority date | — |
| Expiry date | Dec 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/085
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital differential line receiver includes a differential signal to single-ended conversion amplifier coupled to receive a data line and data-complement line of a differential signal; a first termination resistor coupled to the data line of the differential signal; a second termination resistor coupled to the data-complement line of the differential signal; a first impedance-adjusting transistor coupled between the first termination resistor and a common mode line; a second impedance-adjusting transistor coupled between the second termination resistor and the common mode line; a control-voltage generator coupled to sense the common mode line and provide a control voltage, the control voltage generator configured to adjust the control voltage to a voltage level such that a combined impedance of the first termination resistor, the first impedance-adjusting transistor, the second termination resistor, and the second impedance-adjusting transistor matches a specified impedance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.