Configurable write command delay in nonvolatile memory
US11188264B2 · kind B2 · utility
1Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Feb 3, 2020 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Feb 3, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a nonvolatile (NV) memory device with asymmetry between intrinsic read operation delay and intrinsic write operation delay. The system can select to perform memory access operations with the NV memory device with the asymmetry, in which case write operations have a lower delay than read operations. The system can alternatively select to perform memory access operations with the NV memory device where a configured write operation delay that matches the read operation delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.