Obtaining computer crash analysis data
US11188407B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2019 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Aug 30, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1469
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When a computer boots up, a Basic Input/Output System (BIOS) configures system memory to have a crash memory area within the system address map, which can be used by a processor to dump crash memory data. When an error event occurs, the processor can initiate a dump to the crash memory area. Any desired data can be placed into the crash memory area, but typical data can include a state of registers in the processor. The processor then sets a flag, such as an external pin, indicating that the crash memory data is ready to be read. The flag can be read by a secure processor, which then reads the crash memory area at normal memory access speeds using the system bus. For example, the secure processor can access the crash memory area using Direct Memory Access (DMA) reads over a PCIe system bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.