Architecture for microcontroller and method for reading data applied to microcontroller
US11188483B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2020 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | May 26, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture for a microcontroller includes a microcontroller, a system memory, an instruction memory, a data memory, a first bus, and a second bus, where the first and second buses perform functions of a single bus. The microcontroller connects to both buses. The instruction memory and the data memory are connected to the first bus. The system memory is connected to the second bus. The microcontroller transmits and receives data to and from the instruction memory and the data memory through the first bus. The microcontroller transmits and receives data to and from the system memory through the second bus. The instruction memory and the data memory transmit and receive data to and from the system memory through the second bus connected to the first bus, avoiding delays caused by rights and priorities and arbitration of same.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.