Compensating circuit for compensating clock signal and memory device including the same
US11189333B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2020 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Jul 26, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a delay locked loop (DLL), a clock compensating circuit, and a data input/output (I/O) circuit. The DLL outputs a first clock signal and a second clock signal. The clock compensating circuit adjusts a voltage level of an output node and generates an inner clock signal based on the voltage level of the output node. The data I/O circuit outputs data to an outside based on the inner clock signal. The clock compensating circuit includes first and second pulse adjusting circuits. The first pulse adjusting circuit connected to a first output node and outputs a first adjusting current based on the first clock signal and a voltage level of the first output node. The second pulse adjusting circuit connected to a second output node and outputs a second adjusting current based on the second clock signal and a voltage level of the second output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.