Semiconductor structure and fabrication method thereof
US11189495B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 29, 2020 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Sep 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a to-be-etched layer including a first region; forming a first pattern material layer on the to-be-etched layer; forming a sacrificial layer on the first pattern material layer; forming a first opening in the sacrificial layer over the first region, where the first opening exposes a first portion of the first pattern material layer; forming a first doped region in the first pattern material layer using the sacrificial layer as a mask; forming a second opening in the sacrificial layer over the first region, where the second opening exposes a second portion of the first pattern material layer; and forming a second doped region in the first pattern material layer using the sacrificial layer as a mask, where the second doped region is connected with the first doped region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.