Integrated circuit including asymmetric ending cells and system-on-chip including the same
US11189640B2 · kind B2 · utility
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Key dates
| Filing date | May 18, 2020 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | May 18, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/991
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit including first and second macroblocks arranged in a first direction, and a plurality of cells between the first macroblock and the second macroblock, the plurality of cells including at least one first ending cell adjacent to the first macroblock and having a first width in the first direction, at least one second ending cell adjacent to the second macroblock and having a second width different from the first width in the first direction, and at least one standard cell between the at least one first ending cell and the at least one second ending cell may be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.