Semiconductor device
US11190193B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2020 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Mar 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device outputs, as an output signal synchronized to a phase-locked loop clock signal, a synchronized input signal that is synchronized to a reference clock signal of a phase-locked loop circuit. The semiconductor device includes the phase-locked loop circuit, a first flip-flop that receives the input signal in synchronization with the reference clock signal on the basis of a feedback signal inputted to a phase comparator of the phase-locked loop circuit 10, and a second flip-flop that receives an output from the first flip-flop on the basis of the phase-locked loop clock signal. The second flip-flop outputs the output from the first flip-flop as the output signal. A setup time to synchronize the input signal to the phase-locked loop clock signal is set to one half of a period of the reference clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.