Wafer/support arrangement, method for producing the arrangement, and use of the arrangement in the processing of the wafer
US11193208B2 · kind B2 · utility
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15Claims
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Assignee
Inventor
Key dates
| Filing date | Sep 22, 2015 |
| Grant date | Dec 7, 2021 |
| Priority date | — |
| Expiry date | Jul 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/68381
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer/support arrangement, including a wafer, a support system, which includes a support and an elastomer layer, and a connecting layer, wherein the connecting layer is a sol-gel layer. The invention further relates to a coated wafer for a wafer/support arrangement according to the invention, wherein a sol-gel layer is used as a connecting layer for a corresponding wafer/support assembly, and to a method for processing the back side of a wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.