Programming frequently read data to low latency portions of a solid-state storage array
US11194473B1 · kind B1 · utility
14Cited by
47References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2019 |
| Grant date | Dec 7, 2021 |
| Priority date | — |
| Expiry date | Feb 7, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage array controller may receive data to be programmed to a solid-state storage device of a plurality of solid-state storage devices. The storage array controller may identify a type of the data and determine whether to program the data to a low latency portion of the solid-state storage device based on the type of the data. In response to determining to program the data to the low latency portion of the solid-state storage device, the storage array controller may program the data to the low latency portion of the solid-state storage device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.