Semiconductor devices including a gate isolation structure and a gate capping layer including different materials from each other
US11195928B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2020 |
| Grant date | Dec 7, 2021 |
| Priority date | — |
| Expiry date | Mar 18, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is provided including an active region on a substrate A plurality of channel layers is spaced apart on the active region. Gate structures are provided. The gate structures intersect the active region and the plurality of channel layers. The gate structures surround the plurality of channel layers. Source/drain regions are disposed on the active region on at least one side of the gate structures. The source/drain regions contact with the plurality of channel layers. A lower insulating layer is disposed between side surfaces of the gate structures on the source/drain regions. Contact plugs penetrate through the lower insulating layer. The contact plugs contact the source/drain regions. An isolation structure intersects the active region on the substrate and is disposed between the source/drain regions adjacent to each other. Each of the gate structures includes a gate electrode and a gate capping layer including materials different from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.