Semiconductor devices including a stress pattern
US11195952B2 · kind B2 · utility
1Cited by
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20Claims
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Assignee
Inventors
Key dates
| Filing date | May 3, 2019 |
| Grant date | Dec 7, 2021 |
| Priority date | — |
| Expiry date | May 3, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices are provided. A semiconductor device includes a fin structure including a stress structure and a semiconductor region that are sequentially stacked on a substrate. The semiconductor device includes a field insulation layer on a portion of the fin structure. The semiconductor device includes a gate electrode on the fin structure. Moreover, the stress structure includes an oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.