Level shifter
US11196420B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2020 |
| Grant date | Dec 7, 2021 |
| Priority date | — |
| Expiry date | Sep 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35613
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifter includes main and auxiliary level shifters, a switch circuit and a hold circuit. The main level shifter includes NMOS and PMOS transistors in a Differential to Single Ended (D2S) structure. The auxiliary level shifter is connected to an output of the main level shifter and includes NMOS and PMOS transistors. Each of the main and auxiliary level shifters includes internal nodes. The switch circuit settles first nodes of the internal nodes to values to support high speed data transmission, and the hold circuit holds second nodes of the internal nodes to a certain value during low frequency operation. The level shifter receives a serial stream of binary values of core supply voltage, converts the serial stream of binary values from the core supply voltage to an input/output (I/O) voltage, and outputs the serial stream of binary values of the input/output (I/O) voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.