Locking technique for phase-locked loop
US11196429B2 · kind B2 · utility
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3References
17Claims
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Key dates
| Filing date | Jul 27, 2020 |
| Grant date | Dec 7, 2021 |
| Priority date | — |
| Expiry date | Jul 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Locking time for a phase-locked loop is decreased by selectively controlling a division value of the feedback divider during the first division cycle to reduce the initial phase error. The division value of the feedback divider during the first division cycle is selectively set such that the locking phase relationship between the two phase detector input signals is achieved at the end of the first division cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.