Successive approximation register (SAR) analog-to-digital converter (ADC) with noise-shaping property
US11196434B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2020 |
| Grant date | Dec 7, 2021 |
| Priority date | — |
| Expiry date | Oct 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Certain aspects of the present disclosure provide a successive approximation register (SAR) analog-to-digital converter (ADC) implemented with a digital filter for noise shaping. For example, certain aspects provide a circuit for analog-to-digital conversion having: a first digital-to-analog converter (DAC) having an output coupled to a sampling node; a comparator having an input coupled to the sampling node; SAR logic having an input coupled to an output of the comparator and at least one output coupled to an input of the first DAC; a quantizer configured to generate a first digital signal representing a voltage at the sampling node; a digital filter configured to apply a filter to the first digital signal; and a second DAC configured to generate an analog signal representing the filtered first digital signal and provide the analog signal to the sampling node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.