Feedback circuit for a decision feedback equalizer
US11196593B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2020 |
| Grant date | Dec 7, 2021 |
| Priority date | — |
| Expiry date | Jul 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/04
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
One embodiment can provide a sampler for a decision feedback equalizer (DFE). The sampler can include a comparator comprising a resolver and a plurality of amplifiers coupled to the resolver. The plurality of amplifiers are to receive an input signal and one or more feedback signals, and the plurality of amplifiers are coupled to each other in parallel, thereby facilitating a summation of the input signal and the one or more feedback signals. The comparator is to generate an output based on the summation of the input signals and the one or more feedback signals. The sampler can further include an inverter to invert the output of the comparator. The inverted output of the inverter is sent to a tap-1 amplifier to generate a tap-1 feedback signal to be sent to the comparator at a next unit interval (UI).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.