Failure analysis method with improved detection accuracy for advanced technology node
US11199508B1 · kind B1 · utility
1Cited by
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20Claims
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Key dates
| Filing date | Jun 12, 2020 |
| Grant date | Dec 14, 2021 |
| Priority date | — |
| Expiry date | Jun 12, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method includes: determining a defective area in a semiconductor device of a semiconductor wafer; thinning the semiconductor wafer from a backside of the semiconductor wafer; bonding a first substrate to the backside of the semiconductor wafer, wherein the first substrate includes an opening and the defective area is exposed through the opening; and performing a test on the defective area by projecting a light beam from the backside through the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.